參數(shù)資料
型號: MPC8378ECVRAJDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 34/125頁
文件大小: 894K
代理商: MPC8378ECVRAJDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
16
Table 12 provides the PLL lock times.
Input hold time for POR config signals with respect to negation of HRESET
0—
ns
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—4
ns
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 12. PLL Lock Times
Parameter
Min
Max
Unit
Notes
PLL lock times
100
s—
Note:
The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 22, “Clocking,for more information.
Table 11. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Note
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