參數(shù)資料
型號： MPC8377VRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 31/127頁
文件大小： 0K
描述： MPU POWERQUICC II 400MHZ 689PBGA
標準包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
126
Freescale Semiconductor
2
10/2009
In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
In Table 5, “Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.
In Table 5, “Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.
In Table 5, “Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.
In Table 11, removed overbar from CFG_CLKIN_DIV.
In Table 17, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400
μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
In Table 29, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.
In Table 60, Gen 1i/1.5G Transmitter AC Specifications,” and Table 62, Gen 2i/3G Transmitter AC
Specifications,” corrected titles from “Transmitter” to “Receiver”.
In Table 72, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
In Table 74, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
In Table 79, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
In Table 80, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
In Section 20.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,
respectively.
1
02/2009
In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
In Table 5, “Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667 MHz.
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,
MPC837xE Design Checklist.
In Table 21, updated tDDKHCX minimum value for 333 MHz to 2.40.
In Table 72, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 14.
In Table 74, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for
core_clk.
In Table 80, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
Updated part numbering information in AF column in Table 84, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
In Table 85, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
Table 87. Document Revision History (continued)
Revision
Date
Substantive Change(s)
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MPC8377VRAJF 功能描述:微處理器 - MPU PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8377VRAJFA 功能描述:微處理器 - MPU 8377 PBGA ST PbFr No ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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