參數(shù)資料
型號: MPC8377EVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 34/127頁
文件大小: 0K
描述: MPU PWRQUICC II 667MHZ 689TEPBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
14
Freescale Semiconductor
4.1
DC Electrical Characteristics
This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. This table provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.7
OVDD + 0.3
V
Input low voltage
VIL
–0.3
0.4
V
CLKIN Input current
0 V
≤ VIN ≤ OVDD
IIN
—± 10
μA—
PCI_CLK Input current
0 V
≤ VIN ≤ 0.5 V or
OVDD – 0.5 V ≤ VIN ≤ OVDD
IIN
—± 30
μA—
Note:
1. In PCI agent mode, this specification does not comply with
PCI 2.3 Specification.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Note
CLKIN/PCI_CLK frequency
fCLKIN
25
66.666
MHz
1, 6
CLKIN/PCI_CLK cycle time
tCLKIN
15
40
ns
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
60
%
CLKIN/PCI_CLK jitter
± 150
ps
Notes:
1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter-short term and long term-and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low
to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
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