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| 型號(hào)： | MPC8377EVRAGD |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 109/127頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU PWRQUICC II 400MHZ 689TEPBGA |
| 產(chǎn)品培訓(xùn)模塊： | MPC837x PowerQUICC II Pro Processors |
| 視頻文件： | Introduction to the MPC837x Family |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | MPC83xx |
| 處理器類(lèi)型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 689-BBGA 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 689-TEPBGA II（31x31） |
| 包裝： | 托盤(pán) |
| 配用： | MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1 MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
82
Freescale Semiconductor
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
— For external DC-coupled connection, as described in Section 21.2.1, “SerDes Reference
Clock Receiver Characteristics,” the maximum average current requirements sets the
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 53 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 54 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SD _REF_CLK input amplitude
(single-ended swing) must be between 400 mV and 800 mVp-p (from Vmin to Vmax) with
SDn_REF_CLK either left unconnected or tied to ground.
—The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 55
shows the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
Figure 53. Differential Reference Clock Input DC Requirements (External DC-Coupled)
SD
n_REF_CLK
SD
n_REF_CLK
Vmax < 800 mV
Vmin > 0 V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
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