參數(shù)資料
型號(hào)： MPC8377ECVRANGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 35/124頁
文件大?。?/td> 1462K
代理商： MPC8377ECVRANGA
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
18
Freescale Semiconductor
DDR1 and DDR2 SDRAM
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Table 18 provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.
Table 19 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
—
V
Table 18. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
—
V
Table 19. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS-MDQ/MECC/MDM
400 MHz data rate
333 MHz data rate
266 MHz data rate
tCISKEW
–500
–750
500
750
ps
—
Note:
1 t
CISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that will
be captured with MDQS
n. This should be subtracted from the total timing budget.
2 The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
DISKEW. This can be
determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the
absolute value of tCISKEW.
3 This specification applies only to DDR2 interface.
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