參數(shù)資料
型號(hào): MPC8360VVALDHA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA740
封裝: 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740
文件頁(yè)數(shù): 57/102頁(yè)
文件大?。?/td> 606K
代理商: MPC8360VVALDHA
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
58
Freescale Semiconductor
UTOPIA/POS AC Timing Specifications
This figure provides the AC test load for the UTOPIA.
Figure 46. UTOPIA AC Test Load
These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge
of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
This figure shows the UTOPIA timing with external clock.
Figure 47. UTOPIA AC Timing (External Clock) Diagram
UTOPIA inputs—Internal clock input hold time
tUIIXKH
2.4
ns
UTOPIA inputs—External clock input hold time
tUEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA
outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. In rev. 2.0 silicon, due to errata, tUEIVKH minimum is 4.3 ns and tUEIXKH minimum is 1.4 ns under specific conditions. Refer
to Errata QE_UPC3 in Chip Errata for the MPC8360E, Rev. 1.
Table 60. UTOPIA AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
UtopiaCLK (Input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
UTOPIA
Output Signals:
UTOPIA
tUEKHOX
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