參數(shù)資料
型號(hào)： MPC8358VVAGDEA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA740
封裝： 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740
文件頁(yè)數(shù)： 43/102頁(yè)
文件大小： 606K
代理商： MPC8358VVAGDEA
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
45
JTAG AC Electrical Characteristics
10.2
JTAG AC Electrical Characteristics
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)1
At recommended operating conditions (see Table 2).
Parameter
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
033.3
MHz
—
JTAG external clock cycle time
tJTG
30
—
ns
—
JTAG external clock duty cycle
tJTKHKL/tJTG
45
55
%
—
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
—
TRST assert time
tTRST
25
—
ns
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
—
ns
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
11
ns
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
—
ns
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
Figure 22). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect
to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
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