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    參數(shù)資料
    型號(hào): MPC8349ZUALFB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類(lèi): 微控制器/微處理器
    英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
    封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
    文件頁(yè)數(shù): 65/87頁(yè)
    文件大?。?/td> 1037K
    代理商: MPC8349ZUALFB
    MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
    68
    Freescale Semiconductor
    Clocking
    Table 57 provides the operating frequencies for the MPC8349EA TBGA under recommended operating
    conditions (see Table 2).
    All frequency combinations shown in the table below may not be available. Maximum operating
    frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully Addressed by This
    Document,” for part ordering details and contact your Freescale Sales Representative or authorized
    distributor for more information.
    19.1
    System PLL Configuration
    The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor
    encodings for the system PLL.
    Table 57. Operating Frequencies for TBGA
    Characteristic1
    1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,
    LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of
    SCCR[ENCCM], SCCR[USBDRCM] and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
    frequency of the security core and USB modules does not exceed the respective values listed in this table.
    400 MHz
    533 MHz
    667 MHz
    Unit
    e300 core frequency (core_clk)
    266–400
    266–533
    266–667
    MHz
    Coherent system bus frequency (csb_clk)
    100–266
    100–333
    MHz
    DDR1 memory bus frequency (MCK)2
    2 The DDR data rate is 2x the DDR memory bus frequency.
    100–133
    100–166.67
    MHz
    DDR2 memory bus frequency (MCK)3
    3 The DDR data rate is 2x the DDR memory bus frequency.
    100–133
    100–200
    MHz
    Local bus frequency (LCLKn)4
    4 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the
    csb_clk frequency (depending on RCWL[LBIUCM]).
    16.67–133
    MHz
    PCI input frequency (CLKIN or PCI_CLK)
    25–66
    MHz
    Security core maximum internal operating frequency
    133
    166
    MHz
    USB_DR, USB_MPH maximum internal operating frequency
    133
    166
    MHz
    Table 58. System PLL Multiplication Factors
    RCWL[SPMF]
    System PLL Multiplication Factor
    0000
    × 16
    0001
    Reserved
    0010
    × 2
    0011
    × 3
    0100
    × 4
    0101
    × 5
    0110
    × 6
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