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參數(shù)資料
型號(hào)： MPC8349EVVAJFB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/87頁(yè)
文件大小： 0K
描述： IC MPU POWERQUICC II 672-TBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC83xx
處理器類(lèi)型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 672-LBGA
供應(yīng)商設(shè)備封裝： 672-TBGA（35x35）
包裝： 托盤(pán)
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
20
Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 6. Timing Diagram for tDDKHMH
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from
the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
set up (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes
low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the
DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.
See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MDQS
MCK[n]
tMCK
MDQS
tDDKHMH(min) = –0.6 ns
tDDKHMHmax) = 0.6 ns
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