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參數(shù)資料
型號： MPC8349CZUAJFB
廠商： Freescale Semiconductor
文件頁數(shù)： 8/87頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 672TBGA
標準包裝： 24
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 672-LBGA
供應(yīng)商設(shè)備封裝： 672-TBGA（35x35）
包裝： 托盤
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
16
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49
× GV
DD
0.51
× GV
DD
V2
I/O termination voltage
VTT
MVREF –0.04
MVREF +0.04
V
3
Input high voltage
VIH
MVREF +0.18
GVDD +0.3
V
—
Input low voltage
VIL
–0.3
MVREF –0.18
V
—
Output leakage current
IOZ
–9.9
μA4
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
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