參數(shù)資料
型號(hào)： MPC8349CZUAGD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù)： 92/108頁(yè)
文件大?。?/td> 1275K
代理商： MPC8349CZUAGD
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 7
84
Freescale Semiconductor
Clocking
As shown in Figure 39, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the
csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),
which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,
clocking, and initialization in the MPC8349E Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (
÷2) to
create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the
same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])
lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create
the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is
controlled by LCCR[CLKDIV].
In addition, some of the internal units may have to be shut off or operate at lower frequency than the
csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped
register after the device exits reset. Table 52 specifies which units have a configurable clock frequency.
Table 52. Configurable Clock Units
Unit
Default
Frequency
Options
TSEC1
csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
TSEC2, I2C1
csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
Security Core
csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
USB DR, USB MPH
csb_clk/3
Off, csb_clk, csb_clk/2,
csb_clk/3
PCI1, PCI2 and DMA complex
csb_clk
Off,
csb_clk
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8349CZUAGDB 功能描述:微處理器 - MPU 8349 TBGA W/O ENCRYP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8349CZUAGFB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MPC8349CZUAJDB 功能描述:微處理器 - MPU 8349 TBGA W/O ENCRYP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8349CZUAJFB 功能描述:微處理器 - MPU 8349 TBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8349CZUALDB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
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