
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
69
MCAS
AG6
O
GVDD
MCS[0:3]
AE7, AH7, AH4, AF2
O
GVDD
MCKE[0:1]
AG23, AH23
O
GVDD
3
MCK[0:5]
AH15, AE24, AE2, AF14, AE23, AD3
O
GVDD
MCK[0:5]
AG15, AD23, AE3, AG14, AF24, AD2
O
GVDD
Pins Reserved for Future DDR2
(They should be left unconnected for MPC8347)
MODT[0:3]
AG5, AD4, AH6, AF4
—
MBA[2]
AD22
SPARE1
AF12
—
7
SPARE2
AG11
—
6
Local Bus Controller Interface
LAD[0:31]
T4, T5, T1, R2, R3, T2, R1, R4, P1, P2,
P3, P4, N1, N4, N2, N3, M1, M2, M3,
N5, M4, L1, L2, L3, K1, M5, K2, K3, J1,
J2, L5, J3
I/O
OVDD
LDP[0]/CKSTOP_OUT
H1
I/O
OVDD
LDP[1]/CKSTOP_IN
K5
I/O
OVDD
LDP[2]
H2
I/O
OVDD
LDP[3]
G1
I/O
OVDD
LA[27:31]
J4, H3, G2, F1, G3
O
OVDD
LCS[0:3]
J5, H4, F2, E1
O
OVDD
LWE[0:3]/LSDDQM[0:3]/LBS[0:3]
F3, G4, D1, E2
O
OVDD
LBCTL
H5
O
OVDD
LALE
E3
O
OVDD
LGPL0/LSDA10/cfg_reset_source0
F4
I/O
OVDD
LGPL1/LSDWE/cfg_reset_source1
D2
I/O
OVDD
LGPL2/LSDRAS/LOE
C1
O
OVDD
LGPL3/LSDCAS/cfg_reset_source2
C2
I/O
OVDD
LGPL4/LGTA/LUPWAIT/LPBSE
C3
I/O
OVDD
LGPL5/cfg_clkin_div
B3
I/O
OVDD
LCKE
E4
O
OVDD
LCLK[0:2]
D4, A3, C4
O
OVDD
LSYNC_OUT
U3
O
OVDD
LSYNC_IN
Y2
I
OVDD
Table 52. MPC8347E (PBGA) Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes