參數(shù)資料
型號(hào)： MPC8347EZQADDB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封裝： 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁(yè)數(shù)： 97/98頁(yè)
文件大?。?/td> 1084K
代理商： MPC8347EZQADDB
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
97
Document Revision History
3
11/2006
Updated note in introduction.
In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA
parts for all silicon revisions, and 400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3.
In Table 5, “MPC8347EA Typical I/O Power Dissipation,” added GVDD 1.8-V values for DDR2;
added table footnote to designate rates that apply only to the TBGA package.
In Section 23, “Ordering Information,” replicated note from document introduction.
2
8/2006
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in Table 39, “JTAG Interface DC Electrical Characteristics,” to
OVDD –0.3.
In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
In Table 63, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
1
4/2006
Removed Table 20, “Timing Parameters for DDR2-400.”
Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Changed Min and Max values for VIH and VIL in Table 40,“PCI DC Electrical Characteristics.”
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18
Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’
0
3/2006
Initial public release.
Table 72. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
相關(guān)PDF資料
PDF描述
MPC8347ZUALDB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
MPC8347CZQAJFB 32-BIT, 533 MHz, MICROPROCESSOR, PBGA620
MPC8347CZQALDB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA620
MPC8347ECZQADDB 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
MPC8347ECZUADFB 32-BIT, 266 MHz, MICROPROCESSOR, PBGA672
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