參數(shù)資料
型號: MPC8347ECZUAJD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 11/102頁
文件大?。?/td> 1094K
代理商: MPC8347ECZUAJD
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
16
Freescale Semiconductor
DDR SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 4 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 4.
DDR Input Timing Diagram
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
GVDD + 0.3
V
MDQS—MDQ/MECC input skew per byte
333 MHz
266 MHz
tDISKEW
750
1125
ps
1
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 <= n <= 7) or ECC (MECC[{0...7}] if n = 8).
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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