參數(shù)資料
型號: MPC8347ECVRADFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件頁數(shù): 11/98頁
文件大小: 1084K
代理商: MPC8347ECVRADFB
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
19
DDR and DDR2 SDRAM
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (PBGA
package)
tMCK
5—
ns
2
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (TBGA
package)
tMCK
7.5
ns
2
ADDR/CMD/MODT output setup with respect to MCK
tDDKHAS
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
ADDR/CMD/MODT output hold with respect to MCK
tDDKHAX
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
MCS(n) output setup with respect to MCK
tDDKHCS
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
MCS(n) output hold with respect to MCK
tDDKHCX
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
ps
5
400 MHz
700
333 MHz
775
266 MHz
1100
200 MHz
1200
MDQ/MECC/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
400 MHz
700
333 MHz
900
相關(guān)PDF資料
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