參數(shù)資料
型號: MPC8347CZUALF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù): 80/102頁
文件大?。?/td> 1094K
代理商: MPC8347CZUALF
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
79
Clocking
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 56 shows the multiplication factor
encodings for the system PLL.
As described in Section 19, “Clocking,the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 57
and Table 58 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
Table 56. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
× 16
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111
× 7
1000
× 8
1001
× 9
1010
× 10
1011
× 11
1100
× 12
1101
× 13
1110
× 14
1111
× 15
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