參數(shù)資料
型號: MPC8347CVVAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁數(shù): 79/102頁
文件大小: 1094K
代理商: MPC8347CVVAJF
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
78
Freescale Semiconductor
Clocking
Table 54 provides the operating frequencies for the MPC8347E TBGA under recommended operating
conditions (see Table 2).
Table 55 provides the operating frequencies for the MPC8347E PBGA under recommended operating
conditions.
Table 54. Operating Frequencies for TBGA
Characteristic1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (
core_clk)
266–400
266–533
266–667
MHz
Coherent system bus frequency (
csb_clk)
100–266
100–333
MHz
DDR and memory bus frequency (MCLK)2
2 The DDR data rate is 2x the DDR memory bus frequency.
100–133
100–166.67
MHz
Local bus frequency (LCLK
n)3
3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the
csb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
166
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
166
MHz
Table 55. Operating Frequencies for PBGA
Characteristic1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (
core_clk)
200–266
200–333
200–400
MHz
Coherent system bus frequency (
csb_clk)
100–266
MHz
Local bus frequency (LCLK
n)2
2 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the
csb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
MHz
相關(guān)PDF資料
PDF描述
MPC8347ECVRALF 32-BIT, 667 MHz, RISC PROCESSOR, PBGA620
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