參數(shù)資料
型號(hào): MPC8343ZQAGD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 41/80頁(yè)
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤(pán)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
46
Freescale Semiconductor
GPIO
14.2
Timer AC Timing Specifications
Table 44 provides the timer input and output AC timing specifications.
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
15.1
GPIO DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the MPC8343EA GPIO.
15.2
GPIO AC Timing Specifications
Table 46 provides the GPIO input and output AC timing specifications.
Table 44. Timers Input AC Timing Specifications1
Parameter
Symbol2
Min
Unit
Timers inputs—minimum pulse width
tTIWID
20
ns
Notes:
1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external
synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
Table 45. GPIO DC Electrical Characteristics
PArameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 46. GPIO Input AC Timing Specifications1
Parameter
Symbol2
Min
Unit
GPIO inputs—minimum pulse width
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external
synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation.
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