參數(shù)資料
型號(hào)： MPC8323ECVRAFDC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 74/82頁(yè)
文件大小： 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
76
Freescale Semiconductor
System Design Information
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
TJ = TC + (RθJC × PD)
where:
TC = case temperature of the package (°C)
RθJC = junction-to-case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8323E.
24.1
System Clocking
The MPC8323E includes three PLLs.
The system PLL (AVDD2) generates the system clock from the externally supplied CLKIN input.
The frequency ratio between the system and CLKIN is selected using the system PLL ratio
configuration bits as described in Section 22.4, “System PLL Configuration.”
The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 22.5, “Core PLL Configuration.”
The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC
Engine block generates or uses external sources for all required serial interface clocks.
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived
directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 44, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8323ECVRAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323ECZQADDC 功能描述:微處理器 - MPU 8323 PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8323ECZQADDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323ECZQAFDC 功能描述:微處理器 - MPU 8323 PBGA W/ ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8323ECZQAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
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