參數(shù)資料
型號(hào): MPC8321EVRAFDC
廠商: Freescale Semiconductor
文件頁數(shù): 2/82頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
10
Freescale Semiconductor
Clock Input Timing
NOTE
AVDDn (1.0 V) is estimated to consume 0.05 W (under normal operating
conditions and ambient temperature).
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8323E.
NOTE
The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This
should be enforced especially on clock signals. Rise time refers to signal
transitions from 10% to 90% of VCC; fall time refers to transitions from
90% to 10% of VCC.
4.1
DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E.
Local bus I/O
load = 25 pF
1 pair of clocks
66 MHz, 32 bits
0.12
W
PCI I/O load = 30 pF
66 MHz, 32 bits
0.057
W
QUICC Engine block and
other I/Os
UTOPIA 8-bit 31 PHYs
0.041
W
Multiply by
number of
interfaces used.
TDM serial
0.001
W
TDM nibble
0.004
W
HDLC/TRAN serial
0.003
W
HDLC/TRAN nibble
0.025
W
DUART
0.017
W
MIIs
0.009
W
RMII
0.009
W
Ethernet management
0.002
W
USB
0.001
W
SPI
0.001
W
Timer output
0.002
W
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
VIH
2.7
OVDD +0.3
V
Input low voltage
VIL
–0.3
0.4
V
Table 6. Estimated Typical I/O Power Dissipation (continued)
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