參數(shù)資料
型號: MPC8315VRADDA
廠商: Freescale Semiconductor
文件頁數(shù): 17/106頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
18
Freescale Semiconductor
DDR and DDR2 SDRAM
This table provides the PLL lock times.
7
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8315E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
7.1 DDR and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8315E when GVDD(typ) = 1.8 V.
Note:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_SYS_CLKIN_DIV.
2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:3] and CFG_SYS_CLKIN_DIV.
4. The parameter names CFG_SYS_CLKIN_DIV and CFG_CLKIN_DIV are used interchangeably in this document.
Table 10. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Note
System PLL lock times
100
s—
e300 core PLL lock times
100
s—
SerDes (SGMII/PCI Exp Phy) PLL lock times
100
s—
USB phy PLL lock times
100
s—
SATA phy PLL lock times
100
s—
Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49
GVDD
0.51
GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF+ 0.125
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.125
V
Output leakage current
IOZ
–9.9
9.9
A4
Output high current (VOUT = 1.420 V,
GVDD= 1.7V)
IOH
–13.4
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
mA
Table 9. RESET Initialization Timing Specifications (continued)
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