參數(shù)資料
型號(hào): MPC8315EVRAFDA
廠商: Freescale Semiconductor
文件頁數(shù): 78/106頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
73
SPI
21.1
SPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the SPI.
21.2
SPI AC Timing Specifications
This table and provide the SPI input and output AC timing specifications.
This figure provides the AC test load for the SPI.
Figure 56. SPI AC Test Load
Figure 57 and Figure 58 represent the AC timing from Table 67. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Table 66. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.1
NVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
——
±5
A
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 67. SPI AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs valid—master mode (internal clock) delay
tNIKHOV
—6
ns
SPI outputs hold—master mode (internal clock) delay
tNIKHOX
0.5
ns
SPI outputs valid—slave mode (external clock) delay
tNEKHOV
—8.5
ns
SPI outputs hold—slave mode (external clock) delay
tNEKHOX
2—
ns
SPI inputs—master mode (internal clock) input setup time
tNIIVKH
6—
ns
SPI inputs—master mode (internal clock)input hold time
tNIIXKH
0—
ns
SPI inputs—slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—slave mode (external clock) input hold time
tNEIXKH
2—
ns
Note:
1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Output
Z0 = 50
NVDD/2
RL = 50
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