參數(shù)資料
型號(hào): MPC8315ECVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 64/106頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
60
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
15.2.4.1
Spread Spectrum Clock
SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
15.3
SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 49. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express or SGMII) in this document based on the application usage:
Note that external AC Coupling capacitor is required for the above two serial transmission protocols with
the capacitor value defined in specification of each protocol section.
SDn_REF_CLK
50
50
Receiver
Transmitter
TXn
RXn
50
50
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