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參數(shù)資料
| 型號(hào)： | MPC8315ECVRAFDA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/106頁 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 620-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 620-PBGA（29x29） |
| 包裝： | 托盤 |
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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
100
Freescale Semiconductor
System Design Information
25.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink temperature and
then back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RJC x PD)
Where
TC is the case temperature of the package
RJC is the junction-to-case thermal resistance
PD is the power dissipation
26 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8315E.
26.1
System Clocking
The MPC8315E includes two PLLs.
1. The platform PLL (AVDD2) generates the platform clock from the externally supplied
SYS_CLK_IN input. The frequency ratio between the platform and SYS_CLK_IN is selected
using the platform PLL ratio configuration bits as described in Section 24.1, “System PLL
2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 24.2, “Core PLL Configuration.”
26.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD1,AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 63, one to each of the AVDD pins. By providing
independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is
reduced.
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