This table provide" />

          參數(shù)資料
          型號(hào): MPC8315CVRADDA
          廠商: Freescale Semiconductor
          文件頁數(shù): 18/106頁
          文件大?。?/td> 0K
          描述: MPU POWERQUICC II PRO 620-PBGA
          標(biāo)準(zhǔn)包裝: 36
          系列: MPC83xx
          處理器類型: 32-位 MPC83xx PowerQUICC II Pro
          速度: 266MHz
          電壓: 1V
          安裝類型: 表面貼裝
          封裝/外殼: 620-BBGA 裸露焊盤
          供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
          包裝: 托盤
          MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
          Freescale Semiconductor
          19
          DDR and DDR2 SDRAM
          This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
          This table provides the recommended operating conditions for the DDR SDRAM component(s) of the
          MPC8315E when GVDD(typ) = 2.5 V.
          This table provides the DDR capacitance when GVDD(typ) = 2.5 V.
          Note:
          1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
          2. MVREF is expected to be equal to 0.5
          GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
          noise on MVREF may not exceed ±2% of the DC value.
          3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
          equal to MVREF. This rail should track variations in the DC level of MVREF.
          4. Output leakage is measured with all outputs disabled, 0 V
          V
          OUT GVDD.
          Table 12. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
          Parameter/Condition
          Symbol
          Min
          Max
          Unit
          Note
          Input/output capacitance: DQ, DQS
          CIO
          68
          pF
          1
          Delta input/output capacitance: DQ, DQS
          CDIO
          —0.5
          pF
          1
          Note:
          1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
          Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
          Parameter/Condition
          Symbol
          Min
          Max
          Unit
          Note
          I/O supply voltage
          GVDD
          2.3
          2.7
          V
          1
          I/O reference voltage
          MVREF
          0.49
          GVDD
          0.51
          GVDD
          V
          2
          I/O termination voltage
          VTT
          MVREF – 0.04
          MVREF + 0.04
          V
          3
          Input high voltage
          VIH
          MVREF + 0.15
          GVDD + 0.3
          V
          Input low voltage
          VIL
          –0.3
          MVREF – 0.15
          V
          Output leakage current
          IOZ
          –9.9
          A4
          Output high current (VOUT = 1.95 V,
          GVDD = 2.3V)
          IOH
          –16.2
          mA
          Output low current (VOUT = 0.35 V)
          IOL
          16.2
          mA
          Note:
          1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
          2. MVREF is expected to be equal to 0.5
          GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
          noise on MVREF may not exceed ±2% of the DC value.
          3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
          equal to MVREF. This rail should track variations in the DC level of MVREF.
          4. Output leakage is measured with all outputs disabled, 0 V
          V
          OUT GVDD.
          Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Interface
          Parameter/Condition
          Symbol
          Min
          Max
          Unit
          Note
          Input/output capacitance: DQ,DQS
          CIO
          68
          pF
          1
          Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
          Parameter/Condition
          Symbol
          Min
          Max
          Unit
          Note
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          MPC8315CVRAFDA 功能描述:微處理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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          MPC8315ECVRADDA 功能描述:微處理器 - MPU ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
          MPC8315ECVRAFDA 功能描述:微處理器 - MPU ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324