
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
11
Electrical Characteristics
before the core voltage, there may be a period of time when all input and output pins be actively driven
and cause contention and/or excessive current. In order to avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the continuous core voltage (VDDC) before the continuous I/O
voltages (LVDDx_ON and NVDDx_ON) and switchable core voltage (VDD) before the switchable I/O
voltages (GVDD, LVDDx_OFF, and NVDDx_OFF). PORESET should be asserted before the continuous
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see
Figure 3. Once all the power
supplies are stable, wait for a minimum of 32 clock cycles before negating PORESET.
The I/O power supply ramp-up slew rate should be slower than 4V/100
μs, this requirement is for ESD
circuit.
Figure 3 shows the power-up sequencing for switchable and continuous supplies.
Figure 3. Power-Up Sequencing
When switching from normal mode to D3 warm (standby) mode, first turn off the switchable I/O voltage
supply and then turn off the switchable core voltage supply. Similarly, when switching from D3 warm
(standby) mode to normal mode, first turn on the switchable core voltage supply and then turn on the
switchable I/O voltage supply.
CAUTION
When the device is in D3 warm (standby) mode, all external voltage
supplies applied to any I/O pins, with the exception of wake-up pins, must
be turned off. Applying supplied external voltage to any I/O pins, except the
wake up pins, while the device is in D3 warm standby mode may cause
permanent damage to the device.
Continuous I/O Voltage
Continuous Core Voltage
0.7 V
90%
t
V
Switchable I/O Voltage
Switchable Core Voltage (VDD)
0.7 V
90%
t
V
Power sequence for continuous power supplies
Power sequence for switchable power supplies