RGMII and RTBI AC Timing
參數資料
型號： MPC8313VRAFFB
廠商： Freescale Semiconductor
文件頁數： 20/99頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 516PBGA
標準包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA 裸露焊盤
供應商設備封裝： 516-PBGAPGE（27x27）
包裝： 托盤
配用： MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
27
8.2.2
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 30. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
–0.5
—
0.5
ns
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.6
ns
Clock cycle duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
—
53
%
Note:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the RTBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Duty cycle reference is LVDDA/2 or LVDDB/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. The frequency of RX_CLK should not exceed the GTX_CLK125 by more than 300 ppm
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