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參數(shù)資料
| 型號： | MPC8313CZQAGDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, TEPBGAII-516 |
| 文件頁數(shù)： | 91/100頁 |
| 文件大?。?/td> | 1247K |
| 代理商： | MPC8313CZQAGDA |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
90
Freescale Semiconductor
System Design Information
22.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (XCOREVDD and XPADVDD) to
ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling
scheme is outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power
and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10
× 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor from each SerDes supply (XCOREVDD and
XPADVDD) to the board ground plane on each side of the device. This should be done for all
SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
22.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NVDD, GVDD, LVDD, LVDDA, or LVDDB as required.
Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain
unconnected.
Power and ground connections must be made to all external VDD, NVDD, GVDD, LVDD, LVDDA, LVDDB,
and VSS pins of the device.
22.6
Output Buffer DC Impedance
The MPC8313E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD
or VSS. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (see Figure 60). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals
NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8313CZQAGDC | 功能描述:微處理器 - MPU 8313 REV2.2 PB NO EN EXT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8313CZQGDD | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313CZQGDDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313CZQGDDB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8313CZQGDF | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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