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| 型號： | MPC8308VMADD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 473MAPBGA |
| 產(chǎn)品培訓(xùn)模塊： | MPC8308 PowerQUICC II Pro Processor |
| 特色產(chǎn)品： | MPC8308 PowerQUICC? II Pro Processor |
| 標(biāo)準包裝： | 84 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 266MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 473-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 473-MAPBGA（19x19） |
| 包裝： | 托盤 |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
40
Freescale Semiconductor
PCI Express
11.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 28 is specified using the passive compliance/test measurement load
(Figure 29) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram
measured with the compliance/test measurement load (Figure 29) is larger than the minimum receiver eye
diagram measured over a range of systems at the input receiver of any real PCI Express component. The
degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon
parasitic characteristics which cause the real PCI Express component to vary in impedance from the
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. RX component designer should provide additional margin to adequately compensate for the
degraded minimum Receiver eye diagram (shown in Figure 28) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the RX package
and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the
eye diagram.
The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500
consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive
UI in the center of the 3500 UI used for calculating the TX UI.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 29 should be used as
the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 28). If the clocks
to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used
as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect
collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the
median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250
consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in
time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks
to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used
as the reference for the eye diagram.
4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50
to ground for both the D+ and D– line (that is, as measured by a vector
network analyzer with 50-
probes, see Figure 29). Note that the series capacitors, C
TX, is optional for the return loss
measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there
is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at
300 mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
Table 35. Differential Receiver (RX) Input Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Units Note
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| MPC8308VMAFDA | 功能描述:微處理器 - MPU E300 MP PbFr 333 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8308VMAFF | 功能描述:微處理器 - MPU E300 MP 333MHZ RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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