參數(shù)資料
型號(hào)： MPC8272CZQTIEX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, BGA-516
文件頁數(shù)： 55/60頁
文件大?。?/td> 746K
代理商： MPC8272CZQTIEX
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
59
Document Revision History
0.2
12/2003
Table 4: Modification of VDD and VCCSYN to 1.45–1.60 V
Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)
Table 5 and Table 20: Addition of muxed signals
CPCI_HS_ES to PCI_REQ1 (AF14)
CPCI_HS_LED to PCI_GNT1 (AE13)
CPCI_HS_ENUM to PCI_GNT2 (AF21)
Table 5 and Table 20: Modification of PCI signal names for consistency with PCI signal names
on other PowerQUICC II devices:
PCI_CFG0 (PCI_HOST_EN) (AC21)
PCI_CFG1 (PCI_ARB_EN) (AE22)
PCI_CFG2 (DLL_ENABLE) (AE23)
PCI_PAR (AF12)
PCI_FRAME (AD15)
PCI_TRDY(AF16)
PCI_IRDY (AF15)
PCI_STOP (AE15)
DEVSEL (AE14)
PCI_IDSEL (AC17)
PCI_PERR (AD14)
PCI_SERR (AD13)
PCI_REQ0–2 (AAE20, AF14, AB14)
PCI_GNT0–2 (AD20, AE13, AF21)
PCI_RST (AF22)
PCI_INTA (AE21)
PCI_C0-3 (AE12, AF13, AC15, AE18)
PCI_AD0-31
Table 5 and Table 20: Corrected assertion level (added “ “) PCI_HOST_EN (AC21) and
PCI_ARB_EN (AE22)
Table 6: Addition of RθJT and note 4
Sections 4.1–4.5 and 4.7 on thermal characteristics: New
Section 7, “Clock Configuration Modes”: Modification to first paragraph. Note that
PCI_MODCK is a bit in the Hard Reset Configuration Word. It is not an input signal as it is in
the MPC8280 Family and MPC8260 Family.
Table 20: Addition of note 2 to TRST (E21) and PORESET (C24)
Table 20: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.”
Note 4 unchanged.
Table 20: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged.
Table 20: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition
of note 1.
0.1
9/2003
Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine)
Table 5: Addition of note 2 to VIH
Table 5: Changed IOL for 60x signals to 6.0 mA
Modification of note 1 for Table 16, Table 17, Table 18, and Table 19
Table 20: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned
to both CS5 and GND. AD8 is only assigned to CS5.
Table 20: Addition of note 4 to Thermal0 (D19) and Thermal1(J3)
Addition of ZQ package code to Figure 15
0
5/2003
NDA release
Table 22. Document Revision History (continued)
Revision
Date
Substantive Changes
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