參數(shù)資料
型號： MPC8272CZQTIEA
廠商： Freescale Semiconductor
文件頁數(shù)： 19/61頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 516-PBGA
標準包裝： 40
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應商設備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
26
Freescale Semiconductor
AC Electrical Characteristics
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
6.3
JTAG Timings
This table lists the JTAG timings.
Table 15. JTAG Timings1
Parameter
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
033.3
MHz
—
JTAG external clock cycle time
tJTG
30
—
ns
—
JTAG external clock pulse width measured at 1.4V
tJTKHKL
15
—
ns
—
JTAG external clock rise and fall times
tJTGR and
tJTGF
05
ns
6
TRST assert time
tTRST
25
—
ns
3, 6
Input setup times
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
—
ns
4, 7
Input hold times
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
10
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
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