參數(shù)資料
型號(hào)： MPC8270CZUUPEX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 450 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
文件頁數(shù)： 24/80頁
文件大?。?/td> 536K
代理商： MPC8270CZUUPEX
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.8
30
Freescale Semiconductor
Clock Configuration Modes
1101_000
100.0 133.3
2.5
250.0 333.3
3
300.0 400.0
5
50.0
66.7
1101_001
100.0 133.3
2.5
250.0 333.3
3.5
350.0 466.6
5
50.0
66.7
1101_010
100.0 133.3
2.5
250.0 333.3
4
400.0 533.3
5
50.0
66.7
1101_011
100.0 133.3
2.5
250.0 333.3
4.5
450.0 599.9
5
50.0
66.7
1101_100
100.0 133.3
2.5
250.0 333.3
5
500.0 666.6
5
50.0
66.7
1101_101
125.0 166.7
2
250.0 333.3
3
375.0 500.0
5
50.0
66.7
1101_110
125.0 166.7
2
250.0 333.3
4
500.0 666.6
5
50.0
66.7
1110_000
100.0 133.3
3
300.0 400.0
3.5
350.0 466.6
6
50.0
66.7
1110_001
100.0 133.3
3
300.0 400.0
4
400.0 533.3
6
50.0
66.7
1110_010
100.0 133.3
3
300.0 400.0
4.5
450.0 599.9
6
50.0
66.7
1110_011
100.0 133.3
3
300.0 400.0
5
500.0 666.6
6
50.0
66.7
1110_100
100.0 133.3
3
300.0 400.0
5.5
550.0 733.3
6
50.0
66.7
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
1
The “l(fā)ow” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry
guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only.
Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of
the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock mode. For
modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial temperature devices
and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5: for Rev0.1 the minimum
CPU frequency is 250 MHz; for RevA or later the minimum CPU frequency is 150 MHz for commercial temperature devices
and 175 MHz for extended temperature devices.
2
As Table 15 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for lower configurations.
3
MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.
4
60x and local bus frequency. Identical to CLKIN.
5
CPM multiplication factor = CPM clock/bus clock
6
CPU multiplication factor = Core PLL multiplication factor
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3
Bus Clock 4
(MHz)
CPM
Multiplication
Factor 5
CPM Clock
(MHz)
CPU
Multiplication
Factor 6
CPU Clock
(MHz)
PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3]
Low
High
Low
High
Low
High
Low High
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