參數(shù)資料
型號(hào)： MPC8265AZUIFBX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 51/52頁(yè)
文件大?。?/td> 884K
代理商： MPC8265AZUIFBX
MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 1.1
8
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2 lists recommended operational voltage conditions.
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
Figure 2. Overshoot/Undershoot Voltage
Table 2. Recommended Operating Conditions(1)
Notes:
1. Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
Rating
Symbol
Value
Unit
Core supply voltage
VDD
1.7 – 1.9(2)
2. CPU frequency less than or equal to 200 MHz.
1.7–2.1(3)
3. CPU frequency greater than 200 MHz but less than 233 MHz.
1.9 –2.2(4)
4. CPU frequency greater than or equal to 233 MHz.
V
PLL supply voltage
VCCSYN
1.7 – 1.92
1.7–2.13
1.9–2.24
V
I/O supply voltage
VDDH
3.135 – 3.465
V
Input voltage
VIN
GND (-0.3) – 3.465
V
Junction temperature (maximum)
Tj
105(5)
5. Note that for extended temperature parts the range is (-40)T
A
– 105Tj.
°C
Ambient temperature
TA
0–705
°C
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL
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