- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4035 > MPC8264AZUPIBB (Freescale Semiconductor)IC MPU POWERQUICC II 480-TBGA PDF資料下載
參數(shù)資料
| 型號： | MPC8264AZUPIBB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 47/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁
MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2.0
6
Freescale Semiconductor
Features
- Coset removing (programmable by the user)
- Filtering idle/unassigned cells (programmable by the user)
- Performing HEC error detection and single bit error correction (programmable by user)
- Generating loss of cell delineation status/interrupt (LOC/LCD)
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate.
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
– 16-bit counters count
- HEC error cells
- HEC single bit error and corrected cells
- Idle/unassigned cells filtered
- Idle/unassigned cells transmitted
- Transmitted ATM cells
- Received ATM cells
– Maskable interrupt is sent to the host when a counter expires
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported
PCI bridge (MPC8265 and MPC8266 only)
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Periphera
l capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70P525ML55BZI8 | IC SRAM 128KBIT 55NS 144FBGA |
| IDT70P5258ML55BZI8 | IC SRAM 128KBIT 55NS 144FBGA |
| MPC8560VT667LC | IC MPU POWERQUICC III 783-FCPBGA |
| XC4020XL-2PQ240C | IC FPGA C-TEMP 3.3V 2SPD 240PQFP |
| XC4020XL-2PQ208I | IC FPGA I-TEMP 3.3V 2SPD 208PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8264AZUPJDB | 功能描述:微處理器 - MPU POWERQUICC II HIP4 REV B RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8264CVR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8264CZU | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8264VR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8264ZU | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。