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參數(shù)資料
| 型號： | MPC8260AZUPIBB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標準包裝： | 21 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應商設備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8260ADS-TCOM-ND - BOARD DEV ADS POWERQUICC II |
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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Features
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE Std 1149.1 JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
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| MPC8260AZUPJDB | 功能描述:微處理器 - MPU POWERQUICC II HIP4 REV B RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8260CVR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8260CZU | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8260EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Integrated Communications Processor Hardware Specifications |
| MPC8260VR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
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