參數(shù)資料
型號(hào): MPC8247VRP
廠商: Motorola, Inc.
英文描述: MPC8272 PowerQUICC II Family Hardware Specifications
中文描述: MPC8272的PowerQUICC II系列硬件規(guī)格
文件頁(yè)數(shù): 6/56頁(yè)
文件大?。?/td> 539K
代理商: MPC8247VRP
6
Freescale Semiconductor, Inc.
MPC8272 PowerQUICC II Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Overview
Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN
basic rate, ISDN primary rate, and user defined.
Subchanneling on each time slot.
Independent transmit and receive routing, frame synchronization and clocking
Concatenation of any not necessarily consecutive time slots to channels independently
for Rx/Tx
Supports H1,H11, and H12 channels
Allows dynamic allocation of channels
– SCC3 in NMSI mode is not usable when USB is enabled.
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provides management for BRI devices as general-circuit interface (GCI) controllers in
time-division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One I
C controller (identical to the MPC860 I
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to two TDM interfaces
– Supports one group of two TDM channels
– 1024 bytes of SI RAM
— Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,
SCC, SMC, and USB serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
— PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI host bridge or peripheral capabilities
— Includes four DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes the configuration registers required by the PCI standard (which are automatically
loaded from the EPROM to configure the MPC8272) and message and doorbell registers
— Supports the I
2
O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August
3, 1998)
— Support for 66-MHz, 3.3-V specification
— 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port
2
2
C controller)
F
n
.
相關(guān)PDF資料
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