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參數(shù)資料
| 型號(hào)： | MPC8247 |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC8272 PowerQUICC II Family Hardware Specifications |
| 中文描述： | MPC8272的PowerQUICC II系列硬件規(guī)格 |
| 文件頁數(shù)： | 4/56頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | MPC8247 |
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MPC8272 PowerQUICC II Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Overview
Separate PLLs for G2_LE core and for the communications processor module (CPM)
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1,
7:1, and 8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs—up to two external masters
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Eight bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x)
— Dedicated interface logic for SDRAM
Disable CPU mode
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.)
F
Freescale Semiconductor, Inc.
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| MPC8247CVR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
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| MPC8247CVRE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8247CVRI | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8247CVRM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
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