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參數(shù)資料
| 型號： | MPC8245TVV333D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 36/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 333MHZ PPC 352-TBGA |
| 標準包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 333MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應商設備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
41
PLL Configurations
1F
111118
Not usable
Off
Notes:
1. Limited by the maximum PCI input frequency (66 MHz).
2
Limited by the maximum system memory interface operating frequency (100 MHz @ 300 MHz CPU).
3. Limited by the minimum memory VCO frequency (133 MHz).
4. Limited due to the maximum memory VCO frequency (372 MHz).
5. Limited by the maximum CPU operating frequency.
6. Limited by the minimum CPU VCO frequency (360 MHz).
7. Limited by the maximum CPU VCO frequency (maximum marked CPU speed X 2).
8. In clock-off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.
9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).
10. PLL_CFG[0:4] settings not listed are reserved.
11. Multiplier ratios for this PLL_CFG[0:4] setting differ from the MPC8240 and are not backward-compatible.
12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting differs from or does not exist on the MPC8240 and may not be fully
backward-compatible.
13. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is for hardware modeling. The AC timing
specifications in this document do not apply in PLL bypass mode.
15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input
signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is for hardware modeling. The AC
timing specifications in this document do not apply in dual PLL bypass mode.
16. Limited by the maximum system memory interface operating frequency (133 MHz @ 266 MHz CPU).
17. Limited by the minimum CPU operating frequency (100 MHz).
18. Limited by the minimum memory bus frequency (50 MHz).
Table 18. PLL Configurations (333- and 350-MHz Parts)
Ref
PLL_
CFG[0:4] 10,13
333 MHz Part 9
350 MHz Part 9
Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
0
0000012
25–4416
75–132
188–330
25–4416
75–132
188–330
3 (2)
2.5 (2)
1
0000112
25–375,7
75–111
225–333
25–385
75–114
225–342
3 (2)
Table 17. PLL Configurations (266- and 300-MHz Parts) (continued)
Ref. No.
PLL_CFG
[0:4] 10,13
266-MHz Part 9
300-MHz Part 9
Multipliers
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
Periph
Logic/
MemBus
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI-to-
Mem
(Mem
VCO)
Mem-to-
CPU
(CPU
VCO)
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