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參數(shù)資料
| 型號： | MPC8245LZU333B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 940K |
| 代理商： | MPC8245LZU333B |
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MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
15
Electrical and Thermal Characteristics
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation.These graphs
define the areas of DLL locking for various modes. The grey areas represent where the DLL will lock.
17
Frequency of operation (OSC_IN)
25
66
MHz
19
OSC_IN rise and fall times
—
5
ns
7
20
OSC_IN duty cycle measured at 1.4 V
40
60
%
21
OSC_IN frequency stability
—
100
ppm
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figures 5 through 8). Tclk is the period
of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization feedback
loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length
(unloaded PC board runner) corresponds to approximately 1 ns of delay. Tdp(max) and Tdp(min) are dependent on
tap delay. See Table 9 for values of Tdp(max) and Tdp(min). See Figure 7 through Figure 10 for DLL locking ranges.
Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more
details on memory clock design and an explanation of how Tdp is defined.
7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall
times are not tested.
Table 9. Tdp(max) and Tdp(min)
Mode
Tdp(min)
Tdp(max)
Unit
Normal tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0x76 is cleared
7.58
12.97
ns
Maximum tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0x76 is set
8.28
17.57
ns
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristics and Conditions
Min
Max
Unit
Notes
5a
5b
VM
VM = Midpoint Voltage (1.4 V)
2
3
CVIL
CVIH
1
PCI_SYNC_IN
VM
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