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參數(shù)資料
| 型號： | MPC8245ARZU466D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 466 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | TBGA-352 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 152K |
| 代理商： | MPC8245ARZU466D |
MOTOROLA MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series
9
PLL Configuration
1F
1111110
Not usable
Off
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum memory interface operating frequency (133 MHz).
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency (466 MHz).
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (932 MHz).
8. Limited by minimum CPU operating frequency (100 MHz).
9. Limited by minimum memory bus frequency (50 MHz).
10.In clock off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
11.Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
12.PLL_CFG[0:4] settings not listed are reserved.
13.Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backwards-compatible.
14.PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
15.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
16.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in the PLL bypass mode.
17.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the
OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the
processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This
mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply
in the dual PLL bypass mode.
Table 18. PLL Configurations for the 466-MHz Part Offering (continued)
Ref
PLL_CFG[0:4]11,14,15
466-MHz Part 9
Multipliers
PCI Clock Input
(PCI_SYNC_IN)
Range1
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU Clock
Range
(MHz)
PCI-to-Mem
(Mem VCO)
Mem-to-CPU
(CPU VCO)
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| MPC8245LVV300D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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