參數(shù)資料
型號(hào)： MPC8240RZU266X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 279K
代理商： MPC8240RZU266X
MOTOROLA
MPC8240 Hardware Specifications
13
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
1.4.2 Thermal Characteristics
Table 6 provides the package thermal characteristics for the MPC8240.
1.4.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC8240. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Table 7 and Section 1.4.3.1, Clock AC
Specications and tested for conformance to the AC specications for that frequency. The processor core
frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0
4] signals. Parts are sold by maximum processor core frequency; see Section 1.9, Ordering Information.
Table 7 provides the operating frequency information for the MPC8240.
1.4.3.1 Clock AC Specications
Table 8 provides the clock AC timing specications as dened in Section 1.4.3.2.
Table 6. Package Thermal Characteristics
Characteristic
Symbols
Value
Units
Die Junction-to-Case Thermal Resistance
qJC
1.8
C/W
Die Junction-to-Board Thermal Resistance
qJB
4.8
C/W
Notes:
1
Refer to Section 1.7, System Design Information, for more details about thermal management
.
Table 7. Operating Frequency
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Characteristic1
200 MHz
250 MHz
266 MHz
Units
Min
Max
Min
Max
Min
Max
Processor Frequency (CPU)
100
200
100
250
100
266
MHz
Memory Bus Frequency
25 100
MHz
PCI Input Frequency
25 66
MHz
Notes:
1
Caution: The PCI_SYNC_IN frequency and PLL_CFG[04] settings must be chosen such that the
resulting peripheral logic/ memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies
do not exceed their respective maximum or minimum operating frequencies. Refer to the
PLL_CFG[04] signal description in Section 1.6, PLL Conguration, for valid PLL_CFG[04] settings
and PCI_SYNC_IN frequencies.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristics and Conditions 1
Min
Max
Unit
Notes
Frequency of Operation (PCI_SYNC_IN)
25
66
MHz
1
PCI_SYNC_IN Cycle Time
40
15
ns
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