參數(shù)資料
型號： MPC745BVT300LE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA255
封裝： 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, PLASTIC, BGA-255
文件頁數(shù)： 35/60頁
文件大?。?/td> 1559K
代理商： MPC745BVT300LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
40
Freescale Semiconductor
System Design Information
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, L2OVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors:100–330 F (AVX TPS tantalum or Sanyo OSCON).
8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level through a resistor. Unused active low inputs should be tied to OVDD. Unused active high inputs
should be connected to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the
MPC755. Note that power must be supplied to L2OVDD even if the L2 interface of the MPC755 will not
be used; it is recommended to connect L2OVDD to OVDD and L2VSEL to BVSEL if the L2 interface is
unused. (This requirement does not apply to the MPC745 since it has neither an L2 interface nor L2OVDD
pins.)
8.5
Output Buffer DC Impedance
The MPC755 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure
Z0, an external resistor is connected from the chip pad to (L2)OVDD or GND. Then, the value of each
resistor is varied until the pad voltage is (L2)OVDD/2 (see Figure 22).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals (L2)OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,
SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals (L2)OVDD/2. RP then
becomes the resistance of the pull-up devices.
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相關(guān)代理商/技術(shù)參數(shù)
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