參數(shù)資料
型號(hào)： MPC745BPX350LE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 32/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU PPC 350MHZ 255-FCPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 350MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 255-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 255-FCPBGA（21x21）
包裝： 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
38
Freescale Semiconductor
System Design Information
8.2
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC755 to provide power to the clock
generation PLL and L2 cache DLL, respectively. To ensure stability of the internal clock, the power
supplied to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant
frequency range of the PLL. A circuit similar to the one shown in Figure 21 using surface mount capacitors
with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations
of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),
multiple small capacitors of equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. An identical but separate circuit should be placed as close as possible to the L2AVDD pin. It is
often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360
BGA footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is
proportionately less critical.
Figure 21 shows the PLL power supply filter circuit.
Figure 21. PLL Power Supply Filter Circuit
8.3
Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each VDD, OVDD, and L2OVDD pin of the MPC755. It is also recommended that these decoupling
capacitors receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB,
utilizing short traces to minimize inductance.
375
250
188
150
125
400
266
200
160
133
Note: The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not
tested for by the MPC755; see Section 4.2.3, “L2 Clock AC Specifications,” for
valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK
frequencies less than 110 MHz.
Table 17. Sample Core-to-L2 Frequencies (continued)
Core Frequency (MHz)
÷1
÷1.5
÷2
÷2.5
÷3
VDD
AVDD (or L2AVDD)
10
Ω
2.2 F
GND
Low ESL Surface Mount Capacitors
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