參數(shù)資料
型號(hào): MPC745BPX350LE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 350 MHz, RISC PROCESSOR, PBGA255
封裝: 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255
文件頁數(shù): 11/60頁
文件大?。?/td> 1559K
代理商: MPC745BPX350LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
Freescale Semiconductor
19
Electrical and Thermal Characteristics
The L2CLK_OUT timing diagram is shown in Figure 7.
Figure 7. L2CLK_OUT Output Timing Diagram
4.2.4
L2 Bus AC Specifications
Table 12 provides the L2 bus interface AC timing specifications for the MPC755 as defined in Figure 8
and Figure 9 for the loading conditions described in Figure 10.
Table 12. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
tL2CR, tL2CF
—1.0
ns
1
Setup times: Data and parity
tDVL2CH
1.2
ns
2
Input hold times: Data and parity
tDXL2CH
0—
ns
2
Valid times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOV
3.1
3.2
3.3
3.7
ns
3, 4
Output hold times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOX
0.5
0.7
0.9
1.1
ns
3
VM = Midpoint Voltage (L2OVDD/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2 Single-Ended Clock Mode
L2SYNC_OUT
tL2CLK
tCHCL
L2CLK_OUTA
VM
tL2CR
tL2CF
VM
L2CLK_OUTB
VM
tL2CLK
L2SYNC_OUT
VM
tL2CSKW
tCHCL
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