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參數(shù)資料
| 型號： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大小： | 1296K |
| 代理商： | MPC7450RX667LX |
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MPC7450 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
The L3_CLK timing diagram is shown in Figure 7.
.
Figure 7. L3_CLK_OUT Output Timing Diagram
1.5.2.4 L3 Bus AC Specifications
The MPC7450 L3 interface supports three different types of SRAM: source-synchronous, double data rate
(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is
programmed in L3CR[22:23] and the MPC7450 then follows the appropriate protocol for that type. The
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observations about the chip-to-SRAM interface.
The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
For a 1-Mbyte L3, use address bits 0:16 (bit 0 is LSB).
No pull-up resistors are required for the L3 interface.
For high speed operations, L3 interface address and control signals should be a “T” with minimal
stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 8
shows the AC test load for the L3 interface.
Figure 8. AC Test Load for the L3 Interface
L3_CLK0
VM
tL3CR
tL3CF
VM
L3_CLK1
VM
tL3_CLK
tCHCL
VM
tL3CSKW1
L3_ECHO_CLK1
L3_ECHO_CLK3
VM
tL3CSKW2
VM
tL3CSKW2
For PB2 or Late Write:
Output
Z0 = 50
OVDD/2
RL = 50
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