- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45352 > MPC740ARX233TX (FREESCALE SEMICONDUCTOR INC) 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 PDF資料下載
參數(shù)資料
| 型號： | MPC740ARX233TX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 4/44頁 |
| 文件大小： | 558K |
| 代理商： | MPC740ARX233TX |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
12
MPC750A RISC Microprocessor Hardware Specications
Electrical and Thermal Characteristics
1.4.2.2 60x Bus Input AC Specications
Table 9 provides the 60x bus input AC timing specications for the MPC750 as dened in Figure 4 and
Figure 5. Input timing specications for the L2 bus are provided in Section 1.4.2.5, “L2 Bus Input AC
Specications.
Table 9. 60x Bus Input AC Timing Specifications1
At recommended operating conditions (See Table 3)
Num
Characteristic
200, 233, 266 MHz
Unit
Notes
Min
Max
10a
Address/Data/Transfer Attribute Inputs Valid
to SYSCLK (Input Setup)
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input
Setup)
3.0
—
ns
3
10c
Mode select input setup to HRESET
(DRTRY, TLBISYNC)
8—
t
sysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute
Inputs Invalid (Input Hold)
0
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input
Hold)
0
—
ns
3
11c
HRESET to mode select input hold (DRTRY,
TLBISYNC)
0
—
ns
4,6,7
Notes:
1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/Data/Transfer Attribute inputs are composed of the following—A[0–31], AP[0–3], TT[0–4], TBST,
TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other signal inputs are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
6. Guaranteed by design and characterization.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC740ARX266TX | 32-BIT, 266 MHz, RISC PROCESSOR, CBGA255 |
| MPC7410RX450LD | 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410RX400LE | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410RX400LD | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410RX500LC | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7410 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC7410_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7410_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC74-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC74-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。