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| 型號： | MPC740ARX200LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 6/44頁 |
| 文件大小： | 558K |
| 代理商： | MPC740ARX200LX |
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14
MPC750A RISC Microprocessor Hardware Specications
Electrical and Thermal Characteristics
1.4.2.3 60x Bus Output AC Specications
Table 10 provides the 60x bus output AC timing specications for the MPC750 as dened in Figure 6.
Output timing specications for the L2 bus are provided in Section 1.4.2.6, “L2 Bus Output AC
Specications.”
Table 10. 60x Bus Output AC Timing Specifications1
At recommended operating conditions (See Table 3), CL = 50 pF2
Num
Characteristic
200, 233, 266 MHz
Unit
Notes
Min
Max
12
SYSCLK to Output Driven (Output Enable
Time)
0.5
—
ns
13
SYSCLK to Output Valid (TS, ABB, ARTRY,
DBB)
—
6.5
ns
5
14
SYSCLK to all other Outputs Valid (all
except TS, ABB, ARTRY, DBB)
—
6.5
ns
5
15
SYSCLK to Output Invalid (Output Hold)
1.0
—
ns
3
16
SYSCLK to Output High Impedance (all
except ABB, ARTRY, DBB)
—
6.0
ns
8
17
SYSCLK to ABB, DBB High Impedance
after precharge
—
1.0
t
sysclk
4,6,8
18
SYSCLK to ARTRY High Impedance
before precharge
—
5.5
ns
8
19
SYSCLK to ARTRY Precharge Enable
0.2*t
sysclk
+1.0
—
ns
3,4,7
20
Maximum Delay to ARTRY Precharge
—
1
t
sysclk
4,7
21
SYSCLK to ARTRY High Impedance After
Precharge
—2
t
sysclk
4,7,8
Notes:
1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or
2.0 V) of the signal in question. Both input and output timing are measured at the pin.
2. All maximum timing specifications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in
question.
5. Output signal transitions from GND to 2.0V or OVdd to 0.8V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
8. Guaranteed by design and characterization.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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