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參數資料
| 型號： | MPC603EFE133LN |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e Microprocessor(PowerPC 603e微處理器) |
| 中文描述： | 微處理器的PowerPC 603e（PowerPC的603e微處理器） |
| 文件頁數： | 3/5頁 |
| 文件大?。?/td> | 99K |
| 代理商： | MPC603EFE133LN |
PID6-603e Part Number Specifications
3
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
AC Electrical Characteristics
The AC timing speciTcations described in the
Motorola has discontinued the 120MHz offering for the revision described herein. Customers desiring to operate at 120MHz are
encouraged to purchase the 133MHz part. This section provides any other AC electrical characteristics that have been changed for
this revision.
PID6-603e Hardware SpeciTcation
s include 100MHz, 120MHz, and 133MHz.
Clock AC SpeciTcations
The following table provides the revised clock AC timing speciTcations for the parts described herein
Note that the minimum core frequency has been raised from the 16.67MHz value in the Hardware SpeciTcation to 80MHz.
Some parts of this revision manufactured recently will not operate that slowly.
Clock AC Timing Specifications
Vdd = AVdd = 3.3
±
5% V dc, OVdd = 3.3
±
5% V dc, GND = 0 V dc, 0
￡
T
j
￡
105
°
C
Num
Characteristic
100 MHz
133.33 MHz
Unit
Notes
Min
Max
Min
Max
Processor frequency
80
100
120
133.33
MHz
1
VCO frequency
100
200
133.33
266.66
MHz
1
SYSCLK (bus) frequency
16.67
66.67
16.67
66.67
MHz
1
SYSCLK cycle time
15.0
60.0
15.0
60.0
ns
2,3
SYSCLK rise and fall time
2.0
2.0
ns
2
4
SYSCLK duty cycle measured at 1.4 V
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
±
150
±
150
ps
4
Internal PLL relock time
100
100
m
s
3, 5
Notes
1.
Caution
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0D3] signal
description in the hardware speciTcations for valid PLL_CFG[0D3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This speciTcation also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
:
: The SYSCLK frequency and PLL_CFG[0D3] settings must be chosen such that the resulting
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| MPC603ERX100TN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Specifications |
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