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參數(shù)資料
| 型號： | MPC566MZP56 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MCU with Code Compression Option |
| 中文描述： | 32-BIT, FLASH, 56 MHz, RISC MICROCONTROLLER, PBGA388 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MO-151AAL-1, BGA-388 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 109K |
| 代理商： | MPC566MZP56 |
MPC565/MPC566
PRODUCT BRIEF
MOTOROLA
3
22-Channel MIOS timer (MIOS14)
Six modulus counter sub-module (MCSM)
— Four additional MCSM submodules compared to MIOS1
10 double action sub-module (DASM).
12 dedicated PWM sub-modules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
Real-time clock sub-module (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.
Two Queued Analog-to-Digital Converter Modules (QADC64E_A, QADC64E_B)
AMUXes providing a total of 40 analog channels.
40 total input channels on the two modules with internal multiplexing
(AMUXes)
Each QADC64E can see all 40 input channels
10 bit A/D converter with internal sample/hold
Typical conversion time is 4 μs (250-Kbyte samples/sec)
Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
— Periodic/interval timer, assignable to both queue 1 and 2
64 result registers in each QADC64E module
Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
Output data is right or left justified, signed or unsigned
Message Data Link Controller (DLCMD2) Module
Two pins muxed with QSMCM_B pins. Muxing controlled by QSMCM_B PCS3 pin assignment
register
SAE J1850 Class B data communications network interface compatible and ISO compatible for
low-speed (
<
125 Kbps) serial data communications in automotive applications
10.4 Kbps variable pulse width (VPW) bit format
Digital noise filter, collision detection
Hardware cyclical redundancy check (CRC) generation and checking
Block mode receive and transmit supported
4X receive mode supported (41.6 Kbps)
Digital loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
Dedicated register for symbol timing adjustments
Inter-module bus 3 (IMB3) slave interface
Power-saving IMB3 stop mode with automatic wakeup on network activity
Power-saving IMB3 CLOCKDIS mode
Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit
Polling and IMB3 interrupt generation with vector lookup available
Three TouCAN Modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
16 message buffers each, programmable I/O modes
Maskable interrupts
Programmable loop-back for self test operation
Independent of the transmission medium (external transceiver is assumed)
Open network architecture, multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode, with programmable wake up on bus activity
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