
MOTOROLA
Chapter 23. Development Support
23-45
Development Support Registers
Note: These registers are unaffected by reset.
23.6.3
Exception Cause Register (ECR)
The ECR indicates the cause of entry into debug mode. All bits are set by the hardware and
cleared when the register is read when debug mode is disabled, or if the processor is in
debug mode. Attempts to write to this register are ignored. When the hardware sets a bit in
this register, debug mode is entered only if debug mode is enabled and the corresponding
mask bit in the DER is set.
All bits are cleared to zero following reset.
Table 23-17. CMPA-CMPD Bit Descriptions
Bits
Mnemonic
Description
0:31
CMPA-D
Address bits to be compared
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field — RST CHSTP
MCE
—
EXTI ALE PRE FPUVE DECE
—
SYSE
TR
FPASE
SRESET
0000_0000_0000_0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
Field — SEE
—
ITLBER
—
DTLBER
—
LBRK IBRK
EBRK
DPI
SRESET
0000_0000_0000_0000
Addr
SPR 148
Figure 23-16. Exception Cause Register (ECR)
Table 23-18. ECR Bit Descriptions
Bits
Name
Description
0—
Reserved
1
RST
Reset interrupt bit. This bit is set when the system reset pin is asserted.
2
CHSTP
Checkstop bit. Set when the processor enters checkstop state.
3
MCE
Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
4:5
—
Reserved
6
EXTI
External interrupt bit. Set when the external interrupt is asserted.
7
ALE
Alignment exception bit. Set when the alignment exception is asserted.
8
PRE
Program exception bit. Set when the program exception is asserted.
9
FPUVE
Floating point unavailable exception bit. Set when the program exception is asserted.
10
DECE
Decrementer exception bit. Set when the decrementer exception is asserted.